Belkhiri, Hadda (2010) Oppttiimiissaattiioonn ddeess Reessssoouurrcceess ddaannss lleess Syyssttèèmeess Embbaarrqquuééss. Magister thesis, Université de Batna 2.
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Abstract
Recent years have witnessed the emergence of microprocessors that are embedded within a plethora of devices used in everyday life. Embedded architectures are customized through a meticulous criteria and time consuming design process to satisfy stringent constraints with respect to performance, area, power, and cost. In embedded systems, the cost of the memory hierarchy limits its ability to play as central a role. This is due to stringent constraints that fundamentally limit the physical size and complexity of the memory system. Embedded systems are increasingly using on-chip caches as part of their on-chip memory system. The existing cache organization suffers from the inability to distinguish different types of localities. This causes unnecessary movement of data among the levels of the memory hierarchy and increases in miss ratio. In our work we propose split data cache architecture for the embedded multimedia applications that will group memory accesses as scalar or array references according to their inherent locality and will subsequently map each group to a dedicated cache partition
| Item Type: | Thesis (Magister) |
|---|---|
| Uncontrolled Keywords: | Embedded systems, memory hierarchy, Cache misses, Low power design. |
| Subjects: | Informatique |
| Divisions: | Faculté des mathématiques et de l'informatique > Département d'informatique |
| Date Deposited: | 03 Apr 2017 12:12 |
| Last Modified: | 03 Apr 2017 12:12 |
| URI: | http://eprints.univ-batna2.dz/id/eprint/649 |
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